# AMP44 Rev C — Stage 3 digital design report Final validation: 2026-09-11 KST KiCad: 10.0.6 Digital status: **PASS — frozen engineering candidate** Fabrication / assembly status: **not performed** Release sequence: **digital design review complete → fabricator CAM/process confirmation before prototype order → bring-up and measurements after manufacturing** Public-copy note: this report copy corrects the release-gate wording only. The approved Stage-3 board, manufacturing outputs, and three frozen ZIP archives were not regenerated or changed. ## 1. Outcome Stage 3 closes the requested digital PCB findings without changing the schematic circuit: - both OPA1622 inverting feedback sums are manual, F.Cu-only, zero-via routes below 3 mm; - U205/U206/U303/U403 now have direct same-net thermal-via paths and local spreading copper, while U402's existing embedded thermal holes are counted correctly; - balanced and 3.5 mm input ESD paths are explicitly divided into exposed RAW and protected sides, with every clamp reached before the series boundary; - the protected balanced RF network is pair-matched to the stated limits; - the four 2.60 mm mounting apertures are standard NPTH footprints and drill hits rather than ambiguous closed Edge.Cuts contours; - final native board DRC is 0 violations / 0 unconnected, packaged-source DRC is 0 / 0, and packaged-source schematic ERC is 0; - schematic/board/BOM/PnP, connector, thermal, ESD/RF, manufacturing, and DRC policy audits pass. This is a digital sign-off, not evidence that a board has been fabricated or measured. Manufacturing and case packages remain explicitly marked HOLD. ## 2. Frozen baseline and reproducibility The Stage-3 transformation starts from the immutable Stage-2b production board and is implemented by `stage3/apply_stage3_pcb.py`. Because KiCad invalidates some SWIG object proxies after removal, the script intentionally saves and reloads deterministic intermediate boards between these phases: 1. OPA feedback placement and INV_SUM replacement; 2. surrounding-route surgical rip-up and manual rebuild; 3. removal of four Edge.Cuts mounting circles; 4. addition of four standard NPTH mounting footprints; 5. ESD/RF input rework; 6. thermal arrays and filled local copper zones; 7. modification audit. Rejected routing iterations and their DRC JSON are retained in `stage3/evidence/`; only `amp44-revc-stage3.kicad_pcb` is the final candidate. Native DRC converged from 42 violations in the first dense-placement attempt to 0 violations / 0 unconnected in iteration 21. A fresh final DRC was then run on the frozen board and again on the self-contained copy. Hashes: - Stage-2b source board: `b757fdb7885e2a107b808223ef3d236a823de95b7719610c6bd25238cae24966` - Stage-3 final board: `90af5f0c014dd8b71bb18a54b78c51586795ff1fb294ad5dd8ddeab6ac1016b3` The native schematic hierarchy is unchanged from the fully replayed Stage-2a source. Board parity is 228 schematic footprints plus four non-electrical mounting footprints, 140 named nets, and exact value/footprint/pad/net/DNP agreement. ## 3. OPA1622 feedback-loop rework The manufacturer basis is the OPA1622 datasheet guidance to place feedback resistors close to the inverting input and minimize feedback-loop area and parasitic capacitance, cross-checked against the OPA1622EVM layout. Stage-2b had electrically complete but unacceptable long sums: | Net | Before | Stage 3 | Vias | Layer | Result | |---|---:|---:|---:|---|---| | `L_INV_SUM` | 16.4216 mm / 19 segments | 2.9275 mm / 2 segments | 0 | F.Cu | PASS | | `R_INV_SUM` | 13.5145 mm / 14 segments | 2.9275 mm / 2 segments | 0 | F.Cu | PASS | R208 and R211, the feedback resistors, now sit immediately beside the left and right inverting pins. R207/R210 and the surrounding output/supply/monitor copper were also moved or rebuilt so the short sums are real connected copper, not merely favourable straight-line placement measurements. The audit derives path length, segment count, vias, and layers from the final native board. It does not rely on a placement screenshot. Primary evidence: - `stage3/evidence/stage3-modifications.json` - `stage3/evidence/board-audit.json` - `stage3/evidence/critical-route-metrics.csv` ## 4. Direct thermal paths TI's PowerPAD application guidance calls for same-net thermal vias joining the exposed land to internal and opposite-side copper. Stage 3 implements the following direct paths: | Device | EP net | New standalone vias | Via geometry | Spreading copper | |---|---|---:|---|---| | U205 OPA1622 | `-5VA` | 6 | 0.20 mm drill / 0.45 mm land | F.Cu, PWR_SIG, B.Cu | | U206 OPA1622 | `-5VA` | 6 | 0.20 / 0.45 mm | F.Cu, PWR_SIG, B.Cu | | U303 BQ24074 | `AGND` | 4 | 0.20 / 0.45 mm | F.Cu, continuous GND_PLANE, B.Cu | | U403 TPS63031 | `AGND` | 6 | 0.20 / 0.45 mm | F.Cu, continuous GND_PLANE, B.Cu | All 22 new vias are wholly inside their exposed-pad envelopes, carry the same net as the exposed pad, and are marked filled and capped. U205/U206 are explicitly prohibited from touching AGND: their exposed pad is the negative rail, so the arrays and local zones remain `-5VA`. U402 is treated separately. Its footprint already contains six 0.20 mm plated duplicate pad-13 holes on AGND; reporting "zero vias" merely because they are footprint pads rather than standalone PCB vias would be wrong. This is a digital copper/connectivity result. Junction temperature, solder voiding, via fill/cap process, planarization, and real thermal impedance remain fabrication and loaded-test gates. Primary evidence: - `stage3/evidence/thermal-audit.json` - `stage3/sources/TI-SLMA002H-PowerPAD.pdf` ## 5. ESD boundary and protected RF symmetry The audit uses copper-graph shortest paths, not Euclidean distance. For every external input it separately reports: - exposed/unprotected connector-to-TVS and connector-to-series paths; - the explicit series-resistor boundary; - protected series-output paths to shunt capacitors, differential capacitors, receivers, or coupling capacitors; - via count and layer set. ### 5.1 Balanced input All four connector-to-TVS paths are 6.7666–7.4816 mm, a 0.7150 mm four-arm spread, and every TVS is reached before the series-resistor input. The protected network uses exactly two vias in each arm. Protected differential-pair mismatches: | Metric | Left pair | Right pair | Limit | Result | |---|---:|---:|---:|---| | Series output to receiver | 1.6930 mm | 1.1319 mm | < 2 mm | PASS | | Series output to 47 pF shunt | 0.0000 mm | 0.0000 mm | < 2 mm | PASS | | Series output to 220 pF differential capacitor | 1.8849 mm | 1.8310 mm | < 2 mm | PASS | The raw side is deliberately not called length matched. The NBA jack terminals are staggered and the RAW nets include connector escape, clamp tee, and series branch. Raw connector-to-series pair mismatch remains 3.9243 mm left and 1.9799 mm right; aggregate RAW-net copper spread is 9.4027 mm. Those figures are disclosed separately from the actual short clamp path. At the defined protected RF network, pair matching meets the audit contract above. ### 5.2 3.5 mm input D105/D106 physical assignment and RAW routing were corrected so both clamps are reached before their series resistors. Connector-to-TVS paths are 5.8000 and 6.3135 mm, with 0.5135 mm spread. The protected single-ended paths remain on F.Cu with zero vias; no differential-match claim is made for two independent single-ended channels. ### 5.3 Balanced output and shield return All four output clamps are reached before the relay contact and are below 8 mm from their connector terminals. Their lengths are 2.5278–7.4349 mm; the 4.9071 mm spread is disclosed and is not misrepresented as matched. Both outer-layer SHIELD rings are filled and remain isolated from AGND except through the intentional `C111 || R109` coupling. These topology checks do not constitute IEC 61000-4-2 qualification or a claim about real ESD survivability. That requires the finished enclosure, cable, and physical discharge testing. Primary evidence: - `stage3/evidence/esd-rf-audit.json` - `stage3/evidence/esd-rf-paths.csv` ## 6. Mounting-hole normalization The four 2.60 mm closed Edge.Cuts circles were removed and replaced at the same centres by `MH1`–`MH4`, standard non-plated through-hole footprints excluded from BOM and position files. Dimensions and enclosure fastener axes are unchanged. The final NPTH Excellon now contains: - two 0.65 mm USB locating holes; - five 1.20 mm SJ1-3523N locating holes; - four 2.60 mm mounting holes. This eliminates the manufacturing ambiguity between mechanical drilling and internal board routing while preserving the 2.60 mm design intent. ## 7. Final native validation | Check | Final result | |---|---| | Board DRC | 0 violations, 0 unconnected | | Self-contained source DRC | 0 violations, 0 unconnected | | Self-contained schematic ERC | 0 violations | | Board/schematic parity | PASS: 228 electrical + 4 mechanical footprints, 140 nets | | Critical-route audit | PASS, including both 2.9275 mm INV_SUM routes | | Thermal audit | PASS: 22 new vias + 6 existing U402 embedded holes | | Connector/mounting audit | PASS: NBA 22 slots, SJ 3 slots, USB 4 slots, 4 NPTH mounts | | ESD/RF topology audit | PASS with raw-side and output asymmetries disclosed | | Manufacturing audit | PASS | | Case digital geometry | PASS; physical validation INCOMPLETE | Final board inventory: 232 footprints, 690 pads, 1,942 track segments, 168 standalone vias, and 18 filled zones. ### 7.1 Ignored-rule policy audit The KiCad project has no object-level DRC exclusions. Five project-wide categories are inherited as ignored: - footprint filter mismatch; - footprint type mismatch; - missing courtyard; - track endpoint not centred on via; - tuning-profile track geometries. They were audited rather than silently equated with zero findings: - every one of the 232 footprints has the expected side courtyard; - exact schematic-to-board footprint, pad/net, value, and DNP parity passes; - no tuning profile is defined or used; - promoting all ignored categories to error produces 15 findings, all on the new `-5VA` OPA thermal spreading structure and no unconnected items; - in every one, a 0.20 mm trace endpoint is 0.115 mm off the via centre but remains inside the 0.45 mm filled/capped same-net land; same-net solid zones overlap the array as well. Those 15 geometries are accepted as reviewed thermal-array connections, not hidden clearance/short/unconnected errors, and remain disclosed to CAM. The promoted diagnostic is therefore not described as "strict DRC zero"; normal native DRC is the separate 0/0 sign-off. Primary evidence: - `stage3/evidence/drc-final.json` - `stage3/evidence/drc-packaged-source.json` - `stage3/evidence/erc-packaged-source.json` - `stage3/evidence/drc-ignored-promoted.json` - `stage3/evidence/drc-policy-audit.json` ## 8. Manufacturing and assembly package Manufacturing/assembly was exported once, after the Stage-3 board was frozen. No PCB change was made afterward. Package audit summary: - 11 Gerbers and job file; - 230 plated holes and 11 non-plated holes; - 29 PTH routed slots using Excellon `G00/M15/G01/M16` route encoding; - 22 new filled/capped Stage-3 thermal vias represented in the PTH data; - fitted PCBA BOM: 188 references; - native PnP: 157 top + 21 bottom = 178 references; - manual insertion: 10 references; - explicit DNP: R318; - four mechanical mounting references absent from BOM/PnP and present in NPTH; - four-layer 1.60 mm job order: F.Cu / GND_PLANE / PWR_SIG / B.Cu. The 30,886,583-byte STEP contains board body, copper, pads, zones, internal copper, solder mask, and silkscreen. Standard component-body models are absent where the local environment does not contain KiCad package 3D models; this is documented and does not affect fabrication geometry. The inherited board title field still says `Rev C / Stage 2b`, which appears in the Gerber job metadata. The authoritative Stage-3 identifiers are the final board filename/hash, package filenames, manifest schema, and this report. The fabrication notes explicitly forbid substituting the Stage-2b PCB. ## 9. Enclosure impact Stage 3 does not move the board outline, mounting centres, connectors, potentiometer, slide switches, or battery envelope. Therefore the validated Rev-C case package was copied without regenerating geometry; a provenance note records that decision. The existing digital case validation remains: - nine geometry checks pass; - six printable meshes are watertight, consistently wound, single-component, and positive-volume; - maximum battery envelope is 31 × 78 × 9.3 mm with 2.2 mm modeled clearance below the PCB; - all three slider extensions clear full ±1 mm travel; - fixed-component modeled headroom is 4.9 mm; - physical validation remains incomplete. The unchanged fastener axes now correspond to actual 2.60 mm NPTH drill hits. ## 10. Frozen manufacturer references The local primary-source copies used for Stage 3 are: - OPA1622 datasheet SBOS727B: `505556d18113e86aed84f20c1dbcfc6b4ad66ccdc5202998bd883f7a7eac9824` - OPA1622EVM guide SBOU172: `c13108690c0f9ab6c9dfb32c17b99889851b687949fbede1f246047c761b8405` - TI PowerPAD guide SLMA002H: `cdab5db916315b40c6b445a30ccff90de3d391d39231c3f519533113a8cb1f22` ## 11. Release sequence and remaining gates Digital Stage 3 design-file review is complete. The remaining gates occur in this order; a fabricated first article is not a prerequisite for deciding whether to place a prototype order. ### 11.1 Before a prototype order Obtain a fabricator CAM/process confirmation for the 29 routed slots, J102 edge relief, 11 NPTH hits, SHIELD separation, realized stackup, and filled/capped thermal-via process. Confirm the intended slot and hole dimensions against the fabricator's CAM rendering. This is the pre-order decision gate. ### 11.2 After manufacturing and assembly Use the prototype for the tests that require real hardware: 1. insertion gauges for NBA1-24-001, SJ1-3523N, USB-C shell tabs, and plugs; 2. optical/X-ray acceptance for exposed pads and via-in-pad fill/voiding; 3. current-limited USB and battery bring-up with rail, temperature, timer, and protection checks; 4. loaded thermal measurements for OPA1622, charger, and converters; 5. THD+N, noise, oscillation/reactive-load, shutdown transient, relay, and DC protection measurements; 6. printed-case fit, switch force/travel, pot alignment, battery swelling, adhesive, wire bend radius, and fastener validation; 7. physical ESD testing with the final enclosure and cables. Do not connect user earphones until the post-manufacturing bring-up and safety measurements pass. This work performed no fabrication, order, or payment. ## 12. Artifact map - Final native board: `stage3/design/amp44-revc-stage3.kicad_pcb` - Self-contained KiCad project: `stage3/output/design-source/` - Manufacturing package: `stage3/output/manufacturing/` - STEP and native renders: `stage3/output/cad/`, `stage3/output/visuals/` - Rev-C case package: `stage3/output/case/` - Evidence and rejected iterations: `stage3/evidence/` - Replay commands: `stage3/evidence/COMMANDS.md` - Package/root hashes: `stage3/output/SHA256SUMS` The frozen Rev-B tree digest remains `650dd728b04ac2662a307417f324fbed8d90e23260744aed75df08a03dd58bbd`.